VLSI Design

 

 

 

 

Contact person: Dr. Manisha Pattnaik                        Dial: 0751-2449711

 

Objectives and Activities

Research areas of this laboratory include:

-        Rail to rail structure designing

-        Gain boosting techniques

-        Low voltage high gain analogue structures

-        Designing of current mode instrumentation operational amplifier

-        Leakage current analysis and reduction techniques for low power VLSI circuits

-        Power distribution of wireless ad-hoc network with topology control

-        Noise tolerance enhancement techniques for low power and high performance VLSI circuits

-        An efficient energy saving mechanism for IEEE 802.16e wireless MAN

-        Performance evaluation of Deep Submicron Logic Circuits for low voltage, low power and high speed VLSI applications

-        Analysis and designing of low leakage SRAM cells

This laboratory hosts multiple activities like: i) designing and implementation of low power high performance efficient analogue and digital blocks; ii) simulation and modelling of sub 0.1 micron channel MOSFETS.; iii) research on analogue, digital, mixed signal and radio frequency integrated circuits (RFICs) with focus on mobile multimedia, wireless sensor network, and biomedical applications; iv) reconfigurable computing and electronic design automation; and v) CAD for VLSI, VLSI system design, VLSI testing, MOS VLSI designing, low power circuit designing, mixed digital and analogue designing.

 

Infrastructure

Equipments installed in this laboratory include TM 15C and CPLD-XC 9572. Software applications run comprise MINIMOS, Layout editor, Circuit Simulator Pspice, T-spice, Mentor Graphics, Model Sim, and Xilinx ISE.

Room no. C-103 hosts this laboratory.