Teaching Interests :

• Low Power/Low Voltage Electronics
• Nanoscale CMOS Device/Circuits/System Co-Design
• Characterization and Design of Low Power Logic and Memory
• Leakage Power Reduction and Ground Bounce Noise Reduction Techniques
• Power-Gated Arithmetic Circuits for Energy-Precision.
• Process Variation Aware Power Gating Techniques
• Distributed Data-Retention Power Gating Techniques for Embedded SRAM.
• CAD For VLSI
• Noise Removal and Image Enhancement Methods
• Low Power Embedded Multimedia Communication System
• Thermal and Reliability Aware High Performance Energy-Efficient Embedded Computing(HPEEC)

Research Interests  : CMOS, Device/Circuits/System Co-Design, Characterisation and design of Low Power Logic and Memory

Research projects  :

• Co- Principal Investigator of project sponsored by DIT, Govt. of India, Under the scheme of Indian Nanoelectronics user’s Programme, on Characterization of Quantum mechanical Analysis Surrounding Gate Transistor in Nanoscale, 2012-2013
• Principal Investigator of MHRD sponsored project under the Faculty Initiation Grant, ABV-IIITM Gwalior on Design & Simulation of CMOS Technology Based Nanoscale Circuit Architectures for Low Power High Speed Multimedia Products, 2008-2011.
• Project Officer, Research Project sponsored by DOE, New Delhi, Worked on project “Development of CORDIC chips using FPGA and Demonstration of its application in Doppler Ultrasonography” at IIT Kharagpur, 1999.
• Member of Technical Staff, Research Project sponsored by Intel Corporation Worked on project “Low Power Circuits and Systems” at IIT Kharagpur, 2000.

Awards/Honours/Recognision  : Ph.D. (IIT Kharagpur)

Selected Journal Publications:

1. Subhra Dhar,Manisha Pattanaik, P. Rajaram, "Analyzing ION/IOFF in Ultra Deep Submicron CMOS Devices using Grooved nMOSFETs for Low Power Applications", International Journal of Signal and Imaging Systems Engineering, 2012
2. Subhra Dhar, Manisha Pattanaik, P. Rajaram, "Enhanced ION/IOFF in Ultra Deep Submicron CMOS Devices using Grooved nMOSFETs in Comparison to Planar nMOSFET", International Journal of Electronics, Taylor & Francis, 1-13, 2012.
3. Subhra Dhar, Manisha Pattanaik, P. Rajaram, "Evaluating Pathways for Optimised Sub threshold Design: Scaled Bulk nMOSFETs in Deep and Ultradeep Submicron Region", Journal of Computational and Theoretical Nanoscience, American Scientific Publishers (ASP), Vol. 9, 1-8, 2012.
4. Sweta Parashar, Pankaj Srivastava and Manisha Pattanaik, "First-Principles Study of Naphthalene Based Single-Electron Transistor", Applied Nanoscience, DOI 10.1007/s13204-012-0112-x, Springer, 2012.
5. Nafis Uddin Khan, K.V.Arya, Manisha Pattanaik, "A New Adaptive Thresholding in SVD for Efficient Image De-noising", Advances in Intelligent and Soft Computing(VOL.2), pp.659-670, 2012.
6. R.K.Singh, Manisha Pattanaik, Neeraj Kr. Shukla, "Gate Leakage Current Reduction in IP3 SRAM Bit-Cell at 45nm CMOS Technology for Multimedia Applications", Journal of Semiconductor, IOP Science USA, Vol. 33, Issue 4, 2012.
7. Neeraj Kr. Shukla, R.K.Singh, Manisha Pattanaik, "Analysis of Gate Leakage Current in IP3 SRAM Bit-Cell under Temperature Variations in DSM Technology", International Journal of Engineering & Technology (IJET), IACSIT Singapore, Vol. 4, No. 1, 2012.
8. R.K.Singh, Neeraj Kr. Shukla, Manisha Pattanaik, "Characterization of a Novel Low-Power SRAM Bit-Cell Structure at Deep Sub-Micron CMOS Technology for Multimedia Applications",Circuit & Systems, USA, Vol.3., No.1, pp. 23-28, January 2012.
9. Manisha Pattanaik, Neeraj Kr. Shukla, R.K.Singh, "Subthreshold Leakage Current Reduction in IP3 SRAM Bit-Cell at 45nm CMOS Technology for Multimedia Applications", International Journal of Computer Theory and Engineering (IJCET), IACSIT, Singapore, Vol. 3, No. 6, pp. 738-742, Dec. 2011.
10. Chhavi Saxena, Manisha Pattanaik, Kashif Mohd., "A Review of Low Power in CMOS Circuits", International Journal of Communication & Electronics, vol. 6, pp. 39-48 , March 2011.
11. Chhavi Saxena, Manisha Pattanaik, R.K. Tiwari, "Low Power SRAM Cell Design on 90nm CMOS technology with sleep transistors for Low Leakage", ISST Journal of Electricals & Electronics Engineering, vol. 1, pp. 1-10 , Jan-June 2011.
12. Shilpi Birla, Neeraj Kr. Shukla, Kapil Rathi, R.K.Singh, Manisha Pattanaik, "Analysis of 8T SRAM Cell at Various Process Corners at 65nm Process Technology", Circuit & Systems, USA, Vol. 2, No. 4, pp. 326-329, Oct. 2011.
13. Nafis Uddin Khan, K. V. Arya, Manisha Pattanaik, "Image Enhancement and Denoising by Diffusion Based Singular Value Decomposition", International Journal of Computer Applications, Volume 32, No.8, pp14-22, October 2011.
14. Subhra Dhar, Manisha Pattanaik, P. Rajaram, "Relevance of Grooved nMOSFETs in Ultra Deep Submicron Region in Low Power Applications", International Journal of VLSI Design & Communication Systems (VLSICS),Vol.3, No. 3, September 2011.
15. Subhra Dhar, Manisha Pattanaik, P. Rajaram, "Advancements in Nanoscale CMOS Device Design En Route to Ultra Low Power Applications", VLSI Design, Hindawi, Volume 2011, Article ID 178516, 2011.
16. Subhra Dhar, Manisha Pattanaik, P. Rajaram, "Enhanced Leakage Control in Scaled 45 nm NMOS Devices using SiO2 and Si3N4", International Journal of Computer Applications", Vol.29, No. 1, pp. 5-7, 2011.
17. Shilpi Birla, Neeraj Kr. Shukla, Kapil Rathi, R.K.Singh, Manisha Pattanaik, "Stability and Leakage Analysis of a novel PP based 9T SRAM Cell", Circuit & Systems, Scientific Research, USA,2011.
18. Neeraj Kr. Shukla, S. Birla, Manisha Pattanaik, R.K. Singh, "The Effect of Temperature and Vdd on Standby and Leakage Power in a Conventional 6T-SRAM Cell at 90nm and 65nm Technologies", International Journal of Computer Applications (IJCA), USA,Vol.26-No.1, pp-44-48, July 2011.
19. Neeraj Kr. Shukla, R.K.Singh, Manisha Pattanaik, "A Novel Approach to Reduce the Gate and Sub-threshold Leakage in a Conventional SRAM Bit-Cell Structure at Deep-Sub-Micron CMOS Technology", International Journal of Computer Applications (IJCA), USA. Volume 23, No. 7, pp. 23-28 , June 2011.
20. Neeraj Kr. Shukla, R.K.Singh, Manisha Pattanaik, "Design and Analysis of a Novel Low-Power SRAM Bit-Cell Structure at Deep-Sub-Micron CMOS Technology for Mobile Multimedia Applications", International Journal of Advanced Computer Science and Applications (IJACSA), NY, USA, Vol. 2, No. 5, pp. 43-49, May 2011.
21. Neeraj Kr. Shukla, Shilpi Birla, Manisha Pattanaik, R.K. Singh, "Speed and Leakage Power Trade-off in Various SRAM Circuits", International Journal of Computer and Electronics Engineering (IJCEE), IACSIT, Singapore. Vol. 3, No. 2, pp. 244-249, April 2011.
22. Neeraj Kr. Shukla, Shilpi Birla, Manisha Pattanaik, R.K. Singh, "Analysis of the Effects of the Operating Temperature at the Performance and Leakage Power Consumption in a Conventional CMOS 6T-SRAM Bit-Cell at 65nm, 45nm, and 32nm Technologies," IACSIT International Journal of Engineering and Technology, Singapore, Vol.3, No.1, February 2011, pp. 1-9, ISSN: 1793-8236, Jan-June 2011.
23. Shilpi Birla, Neeraj Kr. Shukla, R.K. Singh, Manisha Pattanaik, "Device and Circuit Design Challenges for Low Leakage SRAM for Ultra Low Power Applications", Canadian Journal of Electrical and Electronics Engineering (EEE), Canada, USA, Vol. 1, No. 7, pp. 156-167, December 2010.
24. Shilpi Birla, Neeraj Kr. Shukla, R.K. Singh, Manisha Pattanaik, "Analysis of the Data Stability and Leakage Reduction in the Various SRAM Cells Topologies", International Journal of Engineering Science and Technology (IJEST), Singapore, Vol. 2(7), pp. 2936-2944, ISSN: 0975-5462, July 2010.
25. Chhavi Saxena, Manisha Pattanaik, R.K Tiwari, "A Review of 0.18µm CMOS Full Adders Performance and Analysis", International Journal of Computer science and Engineering", vol. 2, no.1, pp. 189-197, December 2010.
26. Chhavi Saxena, Manisha Pattanaik, R.K Tiwari, " A Review and Comparison of Low Power High Performance Full Adder Cells in 0.18µm and 90nm Technology", International Journal of Industrial Engineering practice, vol. 2,no.2, pp. 71-76, December 2010.
27. Renuraj Garg, Anurag Srivastava, Manisha Pattannaik, "A 0.55-4.3 GHz Low Power and High Swing CMOS Voltage Controlled Ring Oscillator for RF applications", International Journal of Information & Communication Technology, vol. 2, pp. 99-102, 2009.
28. Subodh Thankachan, Manisha Pattanaik, S. S. Rajput, "A ±0.5V BiCMOS Class-A Current Conveyor", International Journal of Electrical Power and Energy system Engineering, vol.2, 2009.
29. Deepak Singhal, Manisha Pattanaik, "A low Voltage low power CMOS based 4GHz VCO for RF Applications", World Academy of Science, Engineering and Technology, 2008, pp.26-32, 2009.
30. Subodh Thankachan, Manisha Pattanaik, S. S. Rajput, "A ±0.5V BiCMOS Class-A Current Conveyor", World Academy of Science, Engineering and Technology, 2008, Vol.31, ISSN 1307-6884, July 2008.
31. Manisha Pattanaik, Swapna Banerjee, Bikram K. Bahinipati, "Power Delay Optimization of Nanoscale CMOS Inverter Using Geometric Programming" WSEAS Transactions on Circuits and Systems, Issue 4, Vol. 5 , 2006.
32. Manisha Pattanaik, Swapna Banerjee, "A New Approach to Analyze a Nanoscale CMOS Buffer", WSEAS Transactions on Circuits and Systems, Issue 2, Vol. 5, 2006.

Selected Conference Publications:

1. R.K.Singh, Manisha Pattanaik, Shilpi Birla, Neeraj Kr. Shukla, Sveen Nagpal, "Analysis and Simulation of a Low-Leakage 10T SRAM Bit-Cell using Dual-Vth Scheme at Deep Sub- Micron CMOS Technology", Proceedings of the International Conference on Advances in Electronics, Electrical and Computer Science Engineering-EEC, 2012.
2. Shilpi Birla, Neeraj Kr. Shukla, Kanishk Sharma, R.K.Singh, Manisha Pattanaik, "Low-Power SRAM Cell at Deep Sub-Micron CMOS Technology for Multimedia Applications", Proceedings of the International Conference on Advances in Electronics, Electrical and Computer Science Engineering-EEC, 2012.
3. Sweta Parashar, Pankaj Srivastava and Manisha Pattanaik, Renormalization of Molecular Energy Levels in Single-Molecule Nanojunctions: An Ab-initio Approach, International Conference on Material Science and Technology (ICMST-12) held at St. Thomas College Pala, Kerala during June 10-14, 2012.
4. Chhavi Saxena, Manisha Pattanaik, R.K. Tiwari, "Enhanced Power Gating Schemes for Low Leakage Low Ground Bounce Noise in Deep Submicron Circuits", International Conference on Devices, Circuits and Systems", ICDCS 2012 , art. no. 6188736 , pp. 239-243, 2012.
5. Manisha Pattanaik, Shashikant Sharma, Anjan Kumar, Balwinder Raj, "Diode Based Trimode Multithreshold CMOS Technique for Ground bounce Noise Reduction in Static CMOS Adders", International Conference on Electronics, Nanomaterials and Components, China, May 2012.
6. Basanta Bhowmik, Manisha Pattanaik, Pankaj Srivastava, "A Tunable Amplifier Using VoltageControlled PseudoResistor for Neural Recording Application " The 2nd International Conference on Electric Technology and CivilEngineering, Three gorges, China, May 18th-20th, 2012.
7. Shashikant Sharma, Anjan Kumar, Manisha Pattanaik, Balwinder Raj, "Forward body Biased Multimode CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders", 4th International Conference on Electronics Computer Technology, Kanyakumari, April 2012.
8. Anjan Kumar, Shashikant Sharma, Manisha Pattanaik, "A Novel Data Preserving Multimode MTCMOS Shift Register for Ground Bounce Noise Minimization", 4th International Conference on Electronics Computer Technology, Kanyakumari, April 2012.
9. Kamal Kishor Jha, Anurag Srivastava, Manisha Pattanaik, Pradip Swarnkar,"Design and estimation of drive current of scaled devices by selection of suitable metal gate with ZrO2 dielectric in nm regime", Proceedings of the International Conference on Nanoscience, Engineering and Technology, ICONSET 2011 , art. no. 6167954 , pp. 202-204, 2011.
10. Deepak Sharma, Manisha Pattanaik, "A Novel High Speed 32 Bit Hybrid Carry Propogate Adder with Eficient Hardware Resource in FPGA", The International Conference on Advances in Computing and Communication, National Institute of Technology, Hamirpur, 2011.
11. Manisha Pattanaik, Shashank Parashar, Chaudhry Indra Kumar, Akanksha Chouhan and Vikas Mahor, "A Novel low Power Noise Tolerant High Performance Dynamic Feed Through Logic Design technique" Proceedings of 2011 IEEE International Symposium on Electronics System Design (ISED), pp. 118-123, December 19-21, 2011 Kochi, India.
12. R.K.Singh, Manisha Pattanaik, Neeraj Kr. Shukla, S. Birla, Naveen Yadav, Ritu, "Analysis and Simulation of Gate Leakage Current in SRAM Bit-Cell at Deep Sub-Micron CMOS Tecnology for Multimedia Applications", Proceedings of international Conference on Advances in Electrical & Electronics 2011, ACEEE-AET, pp. 95-99, Dec. 2011.
13. Chhavi Saxena, Manisha Pattanaik, Shyam Akashe, Kashif Mohd., "Low Ground Bounce Noise and Low Leakage Reduction in Nanometer Regime", International Joint Journal Conference in Computer; Electronics and Electricals", CEE 2011.
14. Manisha Pattanaik, R.K.Singh, Neeraj Kr. Shukla, S. Birla, Geetanjali Dhankar, Pulkit Bhatnagar, "Analysis and Simulation of Sub-threshold Leakage Current in P3 SRAM Cell at DSM CMOS Tecnology for Multimedia Applications", Proceedings of International Conference on Advances in Computer Science 2011, ACEEE-ACS, pp. 107-109, Dec. 2011.
15. Manisha Pattanaik, Satyajeet Sahu, Gaurav Kumar Kashyap, "Improved Stacking Power Gating Technique for Low Leakage Low Ground Bounce Noise Static CMOS Logic Circuits", Proceedings of TENCON 2011 IEEE Region 10 conference, Nov. 21-24, Bali, Indonesia, 2011.
16. Basanta Bhowmik, Manisha Pattanaik, Pankaj Srivastava, "A power efficient nanoscale CMOS Operational for Biomedical Application", National Symposium on Recent advances in Nanoscience , Engineering &Technology(RANET), Nov-19-20, 2011 at ABV-Indian Institute of Information Technology & Management, Gwalior (MP)-India.
17. Sweta Parashar, Pankaj Srivastava and Manisha Pattanaik, "First-Principle Calculations of Charging Energy for Single-Molecule Transistor", Recent Advances in Nanoscience , Engineering & Technology (RANET'11) during Nov.19-20,2011 at ABV-Indian Institute of Information Technology & Management, Gwalior (MP)-India.
18. Vikas Mahor, Akanksha Chouhan and Manisha Pattanaik, "A High Performance Low Power Nano Scale Process Variation Tolerant Wide Fan-In Dynamic OR Gate", Recent Advances in Nanoscience , Engineering & Technology (RANET'11) during Nov.19-20,2011 at ABV-Indian Institute of Information Technology & Management, Gwalior (MP)-India.
19. Basanta Bhowmik, Manisha Pattanaik, Pankaj Srivastava, "A Low Voltage Low Power Nanoscale CMOS Operational Amplifier For Biomedical Signal Recording", Recent Advances in Nanoscience , Engineering & Technology (RANET'11) during Nov.19-20,2011 at ABV-Indian Institute of Information Technology & Management, Gwalior (MP)-India.
20. Jayveer S. Bhadauriya, Pankaj Srivastava and Manisha Pattanaik, "A Layout Aware Leakage Power Reduction Approach In Nano-Multi Threshold CMOS Sequential Circuits", Recent Advances in Nanoscience , Engineering & Technology (RANET'11) during Nov.19-20,2011 at ABV-Indian Institute of Information Technology & Management, Gwalior (MP)-India.
21. Shashikant Sharma, Anjan Kumar, Manisha Pattanaik and Balwinder Raj, "Leakage Current and Ground Bounce Noise Aware Nano-MTCMOS Adder Circuits", Recent Advances in Nanoscience , Engineering & Technology (RANET'11) during Nov.19-20,2011 at ABV-Indian Institute of Information Technology & Management, Gwalior (MP)-India.
22. Shashank Parashar, Chaudhry Indra Kumar, Manisha Pattanaik, "An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise Tolerance", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2011), July 4-6, 2011.
23. Manisha Pattanaik, Nafis uddin Khan, K.V.Arya, "A robust PDE Based Image Denoising Method", Conference Proceedings, IEEE International Conference on Signal Acquistion and Processing.(ICSAP2011), volume 1, pp.136-139, Singapore, Fabruary 26-28, 2011.
24. Subhra Dhar, Manisha Pattanaik, P. Rajaram, "Enhanced ION/IOFF in Ultra Deep Submicron CMOS Devices using Grooved nMOSFETs" International Conference in Electronic Systems, NIT Rourkela, January 2011.
25. Santanu Agnihotri, Manisha Pattanaik, M.V.D.L. Varaprasad, T. Anand Arasu, "Enhanced Ground Bounce Noise Reduction in a Low Leakage 90nm 1-Volt CMOS Full Adder Cell", International Symposium on Electronic System Design (ISED), Bhubaneswar, 20-22 December 2010.
26. Nafis uddin Khan, K.V. Arya, Manisha Pattanaik, "An Efficient Image Noise Removal and Enhancement Method" , Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics ,Instanbul(Turkey) art. no. 5641838 , pp. 3735-3740, 2010.
27. Kamal Kishore Jha, Ankita Jain, Manisha Pattanaik and Anurag Srivastava, "Performance analysis of NMOS for higher speed and low power applications", 2010, 2010 5th International Conference on Future Information Technology, FutureTech 2010 - Proceedings , art. no. 5482680
28. E. Seshadri, Shashikala Tapaswi, Manisha Pattanaik,"SmartCQL: Semantics to handle complex queries over data streams", 2010 6th International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2010 , art. no. 5601127, 2010.
29. Dileep Kumar Jatav, Pankaj Srivastava, "Effect of work function on Double Gate MOSFET", IEEE International Conference of DATICS FutureTech 2010, Busan, South Korea.
30. Nishant Khanwalkar, Shashikala Tapaswi, Manisha Pattanaik "An efficient compressed domain spatial transcoding scheme for adaptive video content delivery", Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 6298 LNCS (PART 2) , pp. 245-251, 2010.
31. Amit Kumar Yadav, Pankaj Kumar, Manisha Pattanaik, "Low Leakage and High Speed Dynamic Thresholdd SRAM(DTSRAM) Design for Deep SubMicron FPGA Applications", 2nd National Conference on Communication Netwrks NCOCN'10, pp.22, 2010, Thrissur, Kerala, India.
32. Deepak Kumar, Pankaj Kumar, Manisha Pattanaik, "Performance analysis of 90nm Look Up Table(LUT) for Low Power Applications", 13th Euromicro Conference On Digital System Design Architectures, Methods and Tools , Lille, France, 1-3 September, 2010.
33. Deepak Kumar, Pankaj Kumar, Manisha Pattanaik, "Performance analysis of dynamic threshold MOS (DTMOS) based 4-input multiplexer switch for low power and high speed FPGA", design, SBCCI'10 - Proceedings of the 23rd Symposium on Integrated Circuits and Systems Design , pp. 2-7 , 2010.
34. M. V. D. L. Varaprasad, Rohit Bapna, Manisha Pattanaik, "Performance Analysis of Low Leakage 1-bit Nano CMOS based Full Adder Cells for Mobile Applications" Proceedings of IEEE International Conference on VLSI Design and Communication Systems, pp. 233-238, Chennai, India, January 2010.
35. Manisha Pattanaik, M.V.D.L. Varaprasad, Fazal Rahim Khan, "Ground Bounce Noise Reduction of 1-bit Nano CMOS based Full Adder Cells for Mobile Applications", Proceedings of IEEE International Conference of Electronic Devices Systems and Applications, Malaysia, April 2010.
36. Manisha Pattanaik, Fazal Rahim Khan, M. V. D. L. Varaprasad, "Improvement of Noise Tolerance Analysis in Deep Submicron Dynamic CMOS Logic Circuits", Proceedings of IEEE International Conference of Electronic Devices Systems and Applications, Malaysia, April 2010.
37. Chhavi Saxena, Manisha Pattanaik, and R. K. Tiwari, "A Review of 0.18µm CMOS Full Adders Performances and Analysis", Proceedings of Recent Trends in Instrumentation, Communication and Microleletronics "INCOMM-10", pp.140-145, April 2010.
38. Chhavi Saxena, Manisha Pattanaik, Kashif Mohd. and Shyam Babu, "A 4x read-power reduction technique in 16Kb 10T SRAM" in National Conf. on recent trend in signal processing & VLSI design, 2010.
39. Kaushik Mazumdar, Manisha Pattanaik, "Noise tolerance enhancement in low voltage dynamic circuits", International Conference on Emerging Trends in Electronic and Photonic Devices & Systems, pp.84-87, 2009.
40. Kaushik Mazumdar, Manisha Pattanaik, "Noise tolerance enhancement in low voltage dynamic circuits", Proceedings of 4th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2009, pp.23-27, April 2009.
41. Kaushik Mazumdar, Manisha Pattanaik, R. Bhanupraksh, "Novel Low Power Noise Tolarant Dynamic Circuit Design Technique", Proceedings of IEEE TENCON Singapore, pp. 1-5, November 23-26, 2009.
42. R. Bhanupraksh, Manisha Pattanaik, S. S. Rajput, and Kaushik Mazumdar, "Analysis and Reduction of Ground Bounce Noise and Leakage Current during Mode Transition of Stacking Power Gating Logic Circuits", Proceedings of IEEE TENCON Singapore, pp.1-6, November 23-26, 2009.
43. Deepak Singhal, Manisha Pattanaik, "A low Voltage low power CMOS based VCO for RF Applications", WSES Transaction on Circuit and Systems, 2009.
44. N. Reddy, Manisha Pattanaik, S.S. Rajput, "0.4V CMOS based low power Voltage Controlled Ring Oscillator for Medical Applications", IEEE Region 10 Annual International Conference, Proceedings/TENCON 2008, art. no. 4766774, 2008.
45. Subodh Thankachan, Manisha Pattanaik, S.S. Rajput, "±0.5V BiCMOS class-A and class-AB current conveyor structures", IEEE Region 10 Annual International Conference, Proceedings/TENCON 2008 , art. no. 4766495, 2008.
46. Subodh Thankachan, Manisha Pattanaik, S.S. Rajput, A new BICMOS Current Conveyor Structure", Proceeding of IEEE Asia Pacific Conference on Circuit and Systems-APCCAS, December 2008.
47. Pooran Singh, Pankaj Kumar, Manisha Pattanaik, and Anurag Shrivastava, "Future Challenges in NANO CMOS Technology: A Brief Review", Proceedings of International Conference on Advances in Nano Technology(ICANAT), MATS University Raipur, November 06-Aug, 2008.
48. Manisha Pattanaik, Swapna Banerjee, "A new approach to model the I/V characteristics for nanoscale MOSFETs", International Symposium on VLSI Technology, Systems, and Applications, pp. 265-268, 2003.
49. Manisha Pattanaik, Swapna Banerjee, "A New Approach to Analyze a Sub-micron CMOS Inverter", "Proceedings of the 16th International Conference on VLSI Design,2003", pp. 116-121, 2003.
50. Manisha Pattanaik, Swapna Banerjee, "Geometric programming based power-delay optimization using transistor-sizing for submicron and deep submicron CMOS inverter ", "TENCON 2003. Conference on Convergent Technologies for Asia-Pacific Region", pp. 484-487, 2003.
51. Manisha Pattanaik, Swapna Banerjee, Bikram K. Bahinipati, "GP based transistor sizing for optimal design of nanoscale CMOS inverter", "2003 Third IEEE Conference on Nanotechnology", pp. 524-527, 2003.

 Achievements

• Programme Committee Member, International Symposium on Electronic System Design (ISED), 21-23 December 2012, Kolkata, India.
• Member, Editorial Board of ISST Journal of Electrical & Electronics Engineering (IJEEE)
• Programme Committee Member, International Conference on Eco-friendly Computing and Communication Systems (ICECCS), 9-11 August 2012, Cochin, Kerala, India.
• Programme Committee Member, International Conference on Advances in Computing & Communications (ACC-2012) 9-11 August 2012, Cochin, Kerala, India.
• Member, Scientific Advisory Board of NCMAT-2012.
• Programme Committee Member, International Symposium on Electronic System Design (ISED), December 2011, Kochi, India.
• Program Committee Member, International Symposium on Electronic System Design (ISED), December 2010, Bhubaneswar, India.
• Session Chair, International Symposium on Electronic System Design (ISED), December 2010, Bhubaneswar, India.
• Member, Institute of Electrical and Electronic Engineers (IEEE).
• Member, Institute of Electronics, Information and Communication Engineers (IEICE).
• Member, Indian Society for Technical Education (ISTE).
• Member, The Institution of Engineers (India)
• Member, World Scientific and Engineering Academy and Society (WSEAS), Greece.
• Referee of IEEE International Conferences on VLSI Design.
• Reviewer, International Journal of Electronics (Taylor and Francis) since 2008