Dr. Gaurav Kaushal received the Ph.D. degree from Indian Institute of Technology Roorkee, and M. Tech. degree from M.A.N.I.T. Bhopal in 2013 and, 2008 respectively. He has authored and co-authored over 40 papers in journals and conference proceedings in various areas of VLSI domain. He has post-doctoral experience in VLSI System Laboratory, Yonsei University, South Korea, from May’2014 to August’2015. He is a member IEEE’ Electronic Devices and IEEE Circuit and System. He is a reviewer of IET Circuits, IEEE TDMR, IEEE Transactions on Electronics Devices, Microelectronics Reliability etc.. He served in National Institute of Technology Patna, India from August’ 2015 – May’2017. Presently he is with ABV-Indian Institute of Information Technology & Management (IIITM), Gwalior, India. His research interests include Analog circuits for bio-medical applications, Low power and Radiation hardened analog and digital circuits, In-memory and near memory computation, AI-accelerator design

ORCID ID : orcid.org/0000-0002-7278-1104

Scopus Author ID : 24178210100

 PUBLICATIONS IN JOURNAL

1. Anil Kumar Rajput, Manisha Pattanaik, Gaurav Kaushal, “Local bit-line shared pass gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture”, in Elsevier Microelectronics Engineering, vol. 129, no. 105569, 2022.
2. S Agrawal, A Srivastava, G Kaushal, A Srivastava, “Edge engineered Graphene Nanoribbons as Nanoscale Interconnect: DFT Analysis” in IEEE Transactions on Nanotechnology, vol. 21, pp. 43-51, 2022.
3. Sonal Agrawal, Anurag Srivastava, Gaurav Kaushal, “Modeling of interface trap charges induced degradation in underlap DG and GAA MOSFETs” Elsevier Microelectronics Reliability, vol. 125, pp. 114344, 2021.
4. Sandeep Semwal, Sonal Agrawal, Anurag Srivastava, Gaurav Kaushal, “Analytical model for quasi-ballistic transport in MOSFET including carrier backscattering” Springer Journal of Computational Electronics, 20, issue 2, 2021, pp. 838-847.
5. Sonal Agrawal, Anurag Srivastava, Gaurav Kaushal, “Understanding electron transport in halogenated graphene nanoribbons and possible application as interconnects” Semiconductor Science and Technology, vol. 37, no. 2, pp. 025004, 2021.
6. Subhajit Dey, Manisha Pattanaik, Gaurav Kaushal, “A low power low noise analog front-end for ECG recording” Springer Analog Integrated Circuits and Signal Processing, vol. 109, 2021, pp. 449–458.
7. CH Naga Raghuram, Bharat Gupta, and Gaurav Kaushal, “Single-Event Multiple Effect Tolerant RHBD14T SRAM Cell Design for Space Applications” in IEEE Transactions on Device and Materials Reliability, vol. 21, no. 1, pp. 48-56, 2021.
8. CH Naga Raghuram,Bharat Gupta, and Gaurav Kaushal, “Double Node Upset Tolerant RHBD15T SRAM Cell Design for Space Applications” in IEEE Transactions on Device and Materials Reliability, 20, no. 1, pp. 181-190, March 2020.
9. Gaurav Kaushal, H. Jeong, Satish Maheshwaram, S. K. Manhas, S. Dasgupta, S. O. Jung, ”Low Power SRAM design for 14nm GAA Si-Nanowire Technology” in Elsevier Microelectronics Engineering, vol. 46, no. 12, pp. 1239-1247, 2015.
10. Gaurav Kaushal, S. K. Manhas, S. Maheshwaram, Dasgupta, B. Anand, and N. Singh, “Novel Design Methodology using L_EXT sizing in Nanowire CMOS Logic” in IEEE Transactions on Nanotechnology, vol. 13, no. 4, pp. 650-658, Jul. 2014.
11. Ravi Shankar, Gaurav Kaushal, , S. Maheshwaram, S. Dasgupta, and S. K. Manhas, “A Degradation Model of Double Gate and Gate-All-Around MOSFETs with Interface Trapped Charges Including Effects of Channel Mobile Charge Carriers” in IEEE Transactions on Device and Materials Reliability , vol. 14, no. 2, pp. 689-697, June, 2014.
12. Maheshwaram, S. K. Manhas, Gaurav Kaushal, B. Anand, and N. Singh, “Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis” in IEEE Transactions on Electron Devices , vol. 60, no. 9, pp. 2943-2950, Sept 2013.
13. Gaurav Kaushal, K. Manhas, S. Maheshwaram, and S. Dasgupta “Impact of Series Resistance on Si Nanowire MOSFET Performance” Springer Journal of Computational Electronics, no. 13, pp. 449-458, March 2013.
14. Gaurav Kaushal, K. Manhas, S. Maheshwaram, S. Dasgupta, B. Anand, and N. Singh, “Tuning Source/Drain Extension Profile for Current Matching in Nanowire CMOS Logic” in IEEE Transactions on Nanotechnology, vol. 11, no. 5, pp. 1033-1039, Sep. 2012.
15. Gaurav Kaushal, S. S. rathod, S. Maheshwaram, S. K. Manhas, A. K. Saxena, and S. Dasgupta, “Radiation Effects in Si-NW GAA FET and CMOS Inverter: A TCAD Simulation Study” in IEEE Transactions on Electron Devices, vol. 59, no. 5, pp. 1563-1566, May 2012.
16. Maheshwaram, S. K. Manhas, Gaurav Kaushal, B. Anand, and N. Singh, “Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform” in IEEE Electron Device Letter, vol. 33, no. 7, pp. 934-936, Jul. 2012.
17. Maheshwaram, S. K. Manhas, Gaurav Kaushal, B. Anand, and N. Singh, “Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS” in IEEE Electron Device Letter, vol. 32, no. 8, pp. 1011-1013, Aug. 2011.

PAPER IN CONFRENCES

1. Noopur Srivastava, Anil Kumar Rajput, Manisha Pattanaik, Gaurav Kaushal, “An Energy-Efficient and Robust 10T SRAM based In Memory Computing Architecture” VLSID-2023, Hyderabad.
2. Shrivas, R. Raj, A. Kumar Rajput, M. pattanaik and G. Kaushal, "Low Noise Amplifier for Health Monitoring," 2021 IEEE Bombay Section Signature Conference (IBSSC), 2021, pp. 1-6.
3. Sonal Agrawal, Anurag Srivastava, Gaurav Kaushal, “Bandgap engineering in Ga and P doped armchair graphene nanoribbons: DFT analysis” Elsevier Materials Today: Proceedings, vol. 48, pp. 647-649, 2022.
4. Sonal Agrawal, Gaurav Kaushal, Anurag Srivastava, “Enhanced metallicity in defected Zigzag graphene nanoribbons: Role of oxygen doping” Springer MRS Advances, vol 6, issue 30, pp. 723-728, 2021.
5. Sonal Agrawal, Anurag Srivastava, Gaurav Kaushal, “Electron Transport in N-functionalised Armchair Graphene Nanoribbons: Computational Insight” IOP Conference Series: Materials Science and Engineering, vol. 1221. pp. 012053, 2022.
6. Sonal Agrawal, Anurag Srivastava, Gaurav Kaushal, “Understanding Electron Transport in oxygen decorated Zigzag Graphene nanoribbons for nanoscale interconnects”, IEEE 21st International Conference on Nanotechnology (NANO), 21-24, 2021.
7. Sonal Agrawal, Anurag Srivastava, Gaurav Kaushal, “N-Doped Zigzag Graphene Nanoribbons for Nanoscale Interconnects, IEEE 10th International Conference Nanomaterials: Applications & Properties (NAP), pp. 01TPNS03-1-01TPNS03-5, doi: 10.1109/NAP51477.2020.9309690, 2020.
8. Bobbili Medha, Durgam Chandana, Veldandi Sowmya, W Wilfred Godfrey, Gaurav Kaushal, Joydip Dhar, “Tumor Growth Modeling and Estimation of Changes with Respect to Cytotoxic Drugs” TENCON 2019-2019 IEEE Region 10 Conference (TENCON), pp. 1053-1058, 2019.
9. Verma, G Kaushal, “Radiation Hardened by Design Sense Amplifier” in International Symposium on VLSI Design and Test (VDAT), 224-235, 2019.
10. Vaishnav Chandak, Priyansh Saxena, Manisha Pattanaik, Gaurav Kaushal, “Semantic image completion and enhancement using deep learning” 10th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2019, pp. 1-6.
11. N. Raghuram, Bharat Gupta, and Gaurav Kaushal, “Analytical modeling of Short channel effects in Nanowire MOSFETs with Interface Trap Charges” in ICAN, India, pp. 1-6, Jan. 2019.
12. Ravish Kumar, Manisha Pattanaik, Gaurav Kaushal, “A Robust SRAM cell for high performance Register File” IEEE International UPCON, Gorakhpur, pp. 1-6, Nov. 2018.
13. N. Raghuram, D. M. Reddy, P. K. Kumar, Gaurav Kaushal, “Robust SRAM Cell Development for Single-Event Multiple Effects” in VDAT, India, pp. 335-347, June 2018.
14. N. Raghuram, P. K. Kumar, Gaurav Kaushal, “Radiation induced SEMU and Process variation analysis of AS8 SRAM cell” in INAC-3, Mohali, pp. 1-6, 2017.
15. Kaushal, H. Jeong, S. O. Jung, Subramanyam, S. N. Rao, Vidya, R. Ramya, S. Shaik and R. Vaddi, "Design and Performance Benchmarking of Steep-Slope Tunnel Transistors for Low Voltage Digital and Analog Circuits Enabling Self-Powered SOCs", Proc. IEEE International SoC Design Conference (ISOCC), South Korea, pp. 32-33, 2014.
16. S Maheshwaram, S. K. Manhas, G. Kaushal, B. Anand, “Vertical nanowire MOSFET parasitic resistance modeling”, IEEE Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, pp. 1-2, 2013.
17. Kaushal, S. Maheshwaram, S. Dasgupta and S. K. Manhas, "Drive Matching Issues in Multi Gate CMOS", in International Conference on Signal Processing and Communication (ICSC), Noida, pp. 349-354, 2013.
18. Gaurav Kaushal, S. Rathod, Satish Maheshwaram, S. K. Manhas, A. K. Saxena and S. Dasgupta, “Single Event Upset in Si Nanowire GAA FET Based CMOS Inverter,” in International Workshop on Physics of Semiconductor Devices (IWPSD), IIT Kanpur, Dec. 2011.
19. Gaurav Kaushal, Satish Maheshwaram, S. Dasgupta and S.K. Manhas, “Analysis of Series Resistance in si-nanowire FET,” in VLSI Design and Test Symposium (VDAT), Pune, 2011.
20. Gaurav Kaushal, Satish Maheshwaram, S. Dasgupta and S.K. Manhas, “Si-Nanowire FET Device and Circuit Performance with progressive technology scaling, Conf. on Communication, Computers, and devices,” IIT Kharagpur, India, pp. 1-6, Dec. 2010.
21. Satish Maheshwaram, Gaurav Kaushal, S. K. Manhas, "A High Performance Vertical Si Nanowire CMOS for Ultra High Density Circuits," Proc. IEEE Asia Pacific Conf. on Circuit and System (APCCAS), pp. 1219-1222, Dec. 2010, Kuala Lumpur, Malaysia.