Academic Credentials

Ph.D.: Indian Institute of Technology, Indore 2016.

M.Tech.: Atal Bihari Vajpayee Indian Institute of Information Technology and Management, Gwalior,  2013.

B.Tech.: Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal, 2011

Sponsored Projects Undertaken:

Project Title: Malware Analysis using machine learning techniques for industrial control systems

Funding Agency: c3iHub, IIT Kanpur

Amount: 15.07 lakhs

Duration: 3 years

 Workshops/FDP organized:

List of Publications

International Journals   :

1. Jai Prakash Kushwaha, Saumya Bhadauria, Shashikala Tapaswi, “mFCBF based Lightweight Intrusion Detection System for IoT Networks”, In Cluster Computing, Springer.(Accepted: Dec 2024)
2. Himanshu Gauttam, K. Pattanaik, Saumya Bhadauria, Garima Nain, “SCL: A sustainable deep learning solution for edge computing ecosystem in smart manufacturing,” in Journal of Industrial Information Integration, Vol. 42, 2024. doi:10.1016/j.jii.2024.100703.
3. Himanshu Gauttam, K. Pattanaik, Saumya Bhadauria, Garima Nain, Putta Bhanu Prakash, “An efficient DNN splitting scheme for edge-AI enabled smart manufacturing,” in Journal of Industrial Information Integration, Vol. 34, 2023. doi: 10.1016/j.jii.2023.100481
4. Jai Prakash Kushwaha, Saumya Bhadauria, Shashikala Tapaswi, “Multi-Method Stacked Feature Selection Approach based IDS for IoT Networks”, in Procedia Computer Science,Vol. 230, 2023, doi:10.1016/j.procs.2023.12.112.
5. Himanshu Gauttam, K. Pattanaik, Saumya Bhadauria, “Cost Aware Topology Formation Scheme for Latency Sensitive Applications in Edge Infrastructure-as-a-Service Paradigm,” in Journal of Network and Computer Applications, Vol. 199, 2022. doi: 10.1016/j.jnca.2021.103303.
6. Pulkit Rathi, Saumya Bhadauria, Sugandha Rathi, “Watermarking of Deep Recurrent Neural Network Using Adversarial Examples to Protect Intellectual Property”, in Applied Artificial Intelligence, Vol. 36 (1), 2022.
7. Anirban Sengupta, Saumya Bhadauria and Saraju P. Mohanty, “Low Cost Security Aware High Level Synthesis Methodology”, IET Computers & Digital Techniques, Volume 11, Issue 2, March 2017.
8. Anirban Sengupta, Saumya Bhadauria and Saraju P. Mohanty, “TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling with Optimal Loop Unrolling Factor during High Level Synthesis”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 4, pp. 655-668, April 2017.
9. Anirban Sengupta, Saumya Bhadauria, “IP core Protection of CDFGs using Robust Watermarking during Behavioral Synthesis Based on User Resource Constraint and Loop Unrolling Factor”, IET Electronics Letters, Vol. 52 No. 6 pp. 439-441, March 2016.
10. Anirban Sengupta, Saumya Bhadauria, “Exploring Low Cost Optimal Watermark for Reusable IP Cores during High Level Synthesis”, IEEE Access Journal, vol. 4, no., pp. 2198-2215, 2016.
11. Anirban Sengupta, Saumya Bhadauria, “Optimized Hardware Design for Trojan Security at Behavioural Level for Loop Based Applications”, Elsevier Journal on VLSI Integration, Invited Paper, Jan 2016.
12. Saumya Bhadauria, Anirban Sengupta “Adaptive bacterial foraging optimization driven Design Space Exploration: Exploring area-performance tradeoff during HLS”, Elsevier Journal on Applied Mathematics and Computations, Volume 269, pp. 265–278, Oct 2015.
13. Anirban Sengupta, Saumya Bhadauria, “Bacterial Foraging Driven Exploration of Multi Cycle Fault Tolerant Datapath based on Power-Performance Tradeoff in High Level Synthesis”, Elsevier Journal on Expert Systems With Applications, Volume 42, pp. 4719 - 4732, Jan 2015.
14. Anirban Sengupta, Saumya Bhadauria, “Automated Design Space Exploration of Multi-Cycle Transient Fault Detectable Datapath based on Multi-Objective User Constraints for Application Specific Computing”, Elsevier Journal on Advances in Engineering Software, Volume 82, pp. 14- 24, April 2015.
15. Saumya Bhadauria, Anirban Sengupta, “Multi-Cycle Single Event Transient Fault Security Aware MO-DSE for Single loop CDFGs in HLS”, IEEE VLSI Circuits & Systems Letters, Volume 1, Issue 2, Oct 2015.
16. Anirban Sengupta, Saumya Bhadauria, “Exploration of Multi-Objective Tradeoff During High Level Synthesis Using Bacterial Chemotaxis and Dispersal”, Elsevier Journal on Procedia Computer Science, Volume 35, Issue C, pp. 63 -72, Sep 2014.

 Conferences :

2. Anirban Sengupta, Saumya Bhadauria, Saraju Mohanty "Embedding Low Cost Optimal Watermark During High Level Synthesis for Reusable IP Core Protection", Proc. of 48^th IEEE Int'l Symposium on Circuits & Systems (ISCAS), Montreal, May 2016.
3. Anirban Sengupta, Saumya Bhadauria, “User Power-Delay Budget Driven PSO Based Design Space Exploration of Optimal k-cycle Transient Fault Secured Datapath during High Level Synthesis”, Proceedings of 16^th IEEE International Symposium on Quality Electronic Design (ISQED), California, USA, March 2015, pp. 289 - 292 (DOUBLE BLIND REVIEW).
4. Anirban Sengupta, Saumya Bhadauria, “Automated Design Space Exploration of Transient Fault Detectable Datapath Based on User Specified Power and Delay Constraints”, Proceedings of 33^rd VLSI - Design Automation & Test (VLSI - DAT),Taiwan, April 2015, pp. 1-4 (DOUBLE BLIND REVIEW).
5. Anirban Sengupta, Saumya Bhadauria “Untrusted Third Party Digital IP cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level Synthesis”,  Proceedings of 25^th IEEE/ACM Great Lake Symposium on VLSI (GLSVLSI), Pennsylvania, May 2015, pp. 167 - 172 (DOUBLE BLIND REVIEW).
6. Anirban Sengupta, Saumya Bhadauria, “Secure Information Processing during System level: Exploration of an Optimized Trojan Secured Datapath for CDFGs during HLS based on User Constraints”, Proceedings of 1^st IEEE iNIS 2015 Dec 2015, pp. 1 – 6.
7. Anirban Sengupta, Saumya Bhadauria, “Automated Exploration of Datapath in High Level Synthesis using Temperature Dependent Bacterial Foraging Optimization Algorithm”, Proceedings of 27th IEEE Canadian Conference on Electrical and Computer Engineering, Toronto, May 2014, pp. 68 -73.
8. Anirban Sengupta, Saumya Bhadauria, “Error Masking of Transient Faults: Exploration of a Fault Tolerant Datapath Based on User Specified Power and Delay Budget”, Proceedings of 13^th IEEE International Conference on Information Technology, Dec 2014, pp. 345 - 350 (DOUBLE BLIND REVIEW).­­

 Achievements  :

• Travel grant by Department of Science and Technology, India for presenting research work in ISQED 2015, California, USA.
• Travel grant by Council of Science and Industrial Research, India for presenting research work in VLSI - DAT,April 2015, Taiwan.
• Travel grant by Asia and South Pacific Design Automation Conference, 2016 for presenting research work in January 2016.
• MHRD Fellowship, Ph.D. (IIT Indore): 2013-2016
• GATE 2011 in Computer Science and Engineering 2011.